Method of fabricating non-volatile memory

ABSTRACT

A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a number of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application of patent application Ser. No.11/162,648, filed on Sep. 18, 2005, now allowed, which claims thepriority benefit of Taiwan patent application serial No. 94107083, filedMar. 9, 2005 and is now patented. The entirety of each of theabove-mentioned patent applications is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device. Moreparticularly, the present invention relates to a non-volatile memory andfabricating method thereof.

2. Description of the Related Art

Among various types of non-volatile memory products, electricallyerasable programmable read only memory (EEPROM) is a memory device thathas been widely used in personal computers and electronic equipment.Data can be stored, read out or erased from the EEPROM many times andstored data are retained even after power supplying the devices is cutoff.

Typically, the floating gate and the control gate of an EEPROM cell arefabricated using doped polysilicon. In the conventional technique, acharge-trapping layer is sometimes used to replace polysiliconfabricated floating gate. The material of the charge-trapping layer issilicon nitride, for example. In general, an oxide layer is formed bothabove and below the silicon nitride charge-trapping layer to form anoxide/nitride/oxide (ONO) composite layer. This type of memory is oftenreferred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memorydevice.

FIG. 1 is a schematic cross-sectional view of a conventionalnon-volatile memory developed in recent years. As shown in FIG. 1, thenon-volatile memory has a memory cell array 117 including a plurality ofmemory cells 102 and a plurality of memory cells 116. The memory cells102 and the memory cells 116 are isolated from one another throughinsulating spacers 110. Each memory cell 102 includes a bottomdielectric layer 104 a, a charge-trapping layer 104 b, a top dielectriclayer 104 c (the bottom dielectric layer 104 a, the charge-trappinglayer 104 b and the top dielectric layer 104 c together form a compositelayer 104), a gate 106 and a mask layer 108 sequentially formed over thesubstrate 100. The memory cells 116 are disposed between every pair ofadjacent memory cells 102. Each memory cell 116 includes a bottomdielectric layer 112 a, a charge-trapping layer 112 b, a top dielectriclayer 112 c (the bottom dielectric layer 112 a, the charge-trappinglayer 112 b and the top dielectric layer 112 c together form a compositelayer 112) and a gate 114 sequentially formed over the substrate 100.Because there is no gap between various memory cells in the non-volatilememory, overall level of integration of the device can be increased.

However, the gates of the memory cells 102 are typically fabricated frompolycide material, for example, formed by a doped polysilicon layer 106a and a silicide layer 106 b. Because the gate 114 of the memory cell116 is formed on a non-planar surface, it is difficult to fill a lowresistant conductive material such as tungsten silicide inside it.Therefore, the gate 114 can only be formed using a higher resistantmaterial such as doped polysilicon. Since doped polysilicon has a higherresistance, the operating speed of the device is limited that it isdifficult to use the device in a high-speed environment.

Furthermore, there is difference in resistance between the materialconstituting the gate 106 of the memory cell 102 and that constitutingthe gate 114 of the memory cell 116. That is, the memory cell 116 has aresistance significantly higher than that of the memory cell 102. As aresult, the electrical properties between the two memory cells aredifferent and may lead to a drop in device performance and stability.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a method offabricating a non-volatile memory that can reduce the gate resistance,improve the electrical performance of the memory cell and increase theefficiency and stability of the device.

The present invention is further directed to a non-volatile memorycapable of resolving the problem of a high resistance in dopedpolysilicon gates and the problem of electrical incompatibility betweenmemory cells.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a method of fabricating a non-volatile memory. First,a substrate is provided. Then, a plurality of first memory units isformed on the substrate. The first memory units are separated from oneanother by a gap. Each first memory unit includes a first compositelayer, a first gate and a cap layer sequentially formed over thesubstrate. Then, a plurality of insulating spacers is formed on thesidewalls of the first memory units. A plurality of second memory unitsis formed in the gap between various first memory units. The secondmemory units together with the first memory units form a memory cellarray. Each second memory unit includes a second composite layer and asecond gate sequentially formed over the substrate. After that, a sourceregion and a drain region are formed in the substrate on the respectivesides of the memory cell array. A first inter-layer insulating layer isformed over the substrate and then the first inter-layer insulatinglayer is patterned to form a first trench and a plurality of secondtrenches. The first trench exposes the source region and the secondtrenches expose the second gates of the second memory units in the samecolumn. A conductive layer is formed over the substrate. The conductivelayer completely fills the first trench and the second trenches. Then, aportion of the conductive layer is removed until the first inter-layerinsulating layer is exposed so that a source line is formed within thefirst trench and a plurality of conductive lines is formed within thesecond trenches. Thereafter, a second inter-layer insulating layer isformed over the substrate and then a conductive plug having a contactwith the drain region is formed in the second inter-layer insulatinglayer and the first inter-layer insulating layer. Lastly, a bit linehaving contact with the conductive plug is formed over the secondinter-layer insulating layer.

According the method of fabricating the non-volatile memory in thepreferred embodiment of the present invention, the first gate can befabricated from a polycide material, the second gate can be fabricatedfrom doped polysilicon and the source line and the conductive lines canbe fabricated from tungsten, for example.

According the method of fabricating the non-volatile memory in thepreferred embodiment of the present invention, the method of removing aportion of the first conductive layer until the first inter-layerinsulating layer is exposed includes performing a chemical-mechanicalpolishing operation.

According the method of fabricating the non-volatile memory in thepreferred embodiment of the present invention, the first composite layerand the second composite layer can be an oxide/nitride/oxide compositelayer.

In the aforementioned method of fabricating the non-volatile memory, theprocess of patterning the first inter-layer insulating layer may includethe fabrication of the first trench and the second trenches. Thereafter,the source line and the plurality of conductive lines for connectingwith the second gates can also be fabricated in the same step. Thus,without increasing the number of processing steps, the electricalresistance of the second gates is reduced and the conductivity of thesecond gates is increased. Ultimately, the electrical performance of thesecond memory units is improved.

The present invention also provides another method of fabricating anon-volatile memory. First, a plurality of first memory units is formedon a substrate. The first memory units are separated from one another bya gap. Each first memory unit includes a first composite layer, a firstgate and a cap layer sequentially formed over the substrate. Then, aplurality of insulating spacers is formed on the sidewalls of the firstmemory units and then a plurality of second memory units is formed inthe gaps between the first memory units. The second memory unitstogether with the first memory units form a memory cell array. Eachsecond memory unit includes a second composite layer and a second gatesequentially formed over the substrate. Then, a source region and adrain region are formed in the substrate on the respective sides of thememory cell array. A first inter-layer insulating layer is formed overthe substrate and then a source line that connects with the sourceregion is formed in the first inter-layer insulating layer. After that,a second inter-layer insulating layer is formed over the firstinter-layer insulating layer. The second inter-layer insulating layerand the first inter-layer insulating layer are patterned to form aplurality of first contact openings and a plurality of second contactopenings. The first contact openings expose the source line and thesecond contact openings expose the second gates of the second memoryunits. Thereafter, a plurality of first conductive plugs is formedinside the first contact openings and a plurality of second conductiveplugs is formed inside the second contact openings. A first conductiveline and a plurality of second conductive lines are formed over thesecond inter-layer insulating layer. The first conductive line connectswith the first conductive plug and the second conductive lines connectwith the second conductive plugs in the same column. A third inter-layerinsulating layer is then formed over the substrate. After that, a thirdconductive plug having contact with the drain region is formed in thethird inter-layer insulating layer, the second inter-layer insulatinglayer and the first inter-layer insulating layer. Lastly, a bit linehaving contact with the third conductive plug is formed over the thirdinter-layer insulating layer.

According to the method of fabricating a non-volatile memory in thepreferred embodiment of the present invention, the first conductive plugand the second conductive plug are fabricated using tungsten and thefirst conductive line and the second conductive line are fabricatedusing copper-aluminum alloy, for example.

According to the method of fabricating a non-volatile memory in thepreferred embodiment of the present invention, the first composite layerand the second composite layer are oxide/nitride/oxide composite layers.

In the aforementioned method of fabricating a non-volatile memory, asecond conductive plug is formed at a distance of several second memoryunits away. The second conductive plug can be fabricated together withthe first conductive plug for connecting with the source line. Hence,the processing step is simplified and the gate conductivity of thesecond memory units is increased so that the electrical performance ofthe second memory units is improved. As a result, the difference inelectrical properties between the second memory units and the firstmemory units is minimized and hence the efficiency and stability of thedevice is raised.

The present invention also provides a non-volatile memory structure. Thenon-volatile memory includes a substrate, a plurality of first memoryunits, a plurality of second memory units, a plurality of insulatingspacers, a source region, a drain region, a first inter-layer insulatinglayer, a source line, a metallic line, a second inter-layer insulatinglayer and a bit line. The first memory units are disposed on thesubstrate and the first memory units are separated from one another by agap. Each first memory unit includes a composite layer, a first gate anda cap layer sequentially formed over the substrate. The second memoryunits are disposed in the gaps between the first memory units. Thesecond memory units together with the first memory units form a memorycell column. Each second memory unit includes a second composite layerand a second gate sequentially formed over the substrate. The insulatingspacers are disposed between the first memory units and the secondmemory units. The source region and the drain region are disposed in thesubstrate on the respective sides of the memory cell column. The firstinter-layer insulating layer is disposed on the substrate and the sourceline is disposed within the first inter-layer insulating layer forconnecting with the source region. The metallic lines are disposed inthe first inter-layer insulating layer and aligned in a directionperpendicular to the memory cell column. Each metallic line is connectedto the second gate of a corresponding second memory unit. The secondinter-layer insulating layer is disposed on the first inter-layerinsulating layer. The bit line is disposed on the second inter-layerinsulating layer and electrically connected to the drain region througha conductive plug.

According to the non-volatile memory in the preferred embodiment of thepresent invention, the first gate is fabricated using a polycidematerial, the second gate is fabricated using doped polysilicon and thesource line and metallic line are fabricated using tungsten, forexample.

The present invention also provides an alternative non-volatile memorystructure. The non-volatile memory includes a substrate, a plurality offirst memory units, a plurality of second memory units, a plurality ofinsulating spacers, a source region, a drain region, a first inter-layerinsulating layer, a source line, a second inter-layer insulating layer,a third inter-layer insulating layer, a first conductive line, aplurality of second conductive lines and a bit line. The first memoryunits are disposed on the substrate and the first memory units areseparated from one another by a gap. Each first memory unit includes afirst composite layer, a first gate and a cap layer sequentially formedover the substrate. The second memory units are disposed in the gapsbetween the first memory units. The second memory units together withthe first memory unit form a memory cell column. Each second memory unitincludes a second composite layer and a second gate. The insulatingspacers are disposed between the first memory units and the secondmemory units. The source region and the drain region are disposed in thesubstrate on the respective sides of the memory cell column. The firstinter-layer insulating layer is disposed on the substrate. The sourceline is disposed in the first inter-layer insulating layer forconnecting with the source region. The second inter-layer insulatinglayer is disposed on the first inter-layer insulating layer and thethird inter-layer insulating layer is disposed on the second inter-layerinsulating layer. The first conductive line is disposed in the thirdinter-layer insulating layer and electrically connected the source linethrough a first conductive plug in the second inter-layer insulatinglayer. The second conductive lines are disposed in the third inter-layerinsulating layer. The second conductive lines are connected to varioussecond gates through a plurality of second conductive plugs in the firstinter-layer insulating layer and the second inter-layer insulatinglayer. The bit line is disposed on the third inter-layer insulatinglayer and electrically connected to the drain region through a thirdconductive plug.

According to the non-volatile memory in the preferred embodiment of thepresent invention, the first conductive plug and the second conductiveplug are fabricated using tungsten, for example. The first conductiveline and the second conductive line are fabricated using copper-aluminumalloy, for example. The first composite layer and the second compositelayer are oxide/nitride/oxide composite layers, for example.

The non-volatile memory in the present invention uses conductive linesto connect with the second gates. Since the conductive lines arefabricated using a metallic or alloy material, the electrical resistanceof the second gates? is reduced and the electrical properties of thesecond memory units are improved. Consequently, the difference inelectrical performance between the first memory units and the secondmemory units is minimized. Ultimately, the efficiency and stability ofthe device is raised.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross-sectional view of a conventionalnon-volatile memory.

FIGS. 2A through 2E are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to one preferredembodiment of the present invention.

FIGS. 3A through 3D are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to anotherpreferred embodiment of the present invention.

FIG. 3E is a top view of a non-volatile memory according to onepreferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIGS. 2A through 2E are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to one preferredembodiment of the present invention.

As shown in FIG. 2A, a substrate 200 is provided. Then, a plurality ofmemory units 202 is formed on the substrate 200. The memory units 202are separated from one another by a gap 209. Each memory unit 202includes a composite layer 204, a gate 206 and a cap layer 208sequentially formed over the substrate 200. The memory units 202 areformed, for example, by depositing composite dielectric material,conductive material and insulating material over the substrate andpatterning the aforementioned material layers by performingphotolithographic and etching processes.

The composite layer 204 includes a bottom dielectric layer 204 a, acharge-trapping layer 204 b and a top dielectric layer 204 c, forexample. The bottom dielectric layer 204 a is a silicon oxide layerformed, for example, by performing a thermal oxidation process. Thecharge-trapping layer 204 b is a silicon nitride layer formed, forexample, by performing a chemical vapor deposition process. The topdielectric layer 204 c is a silicon oxide layer formed, for example, byperforming a chemical vapor deposition process. Obviously, the bottomdielectric layer 204 a and the top dielectric layer 204 c can befabricated using other material having similar properties. The materialconstituting the charge-trapping layer 204 b is also not limited tosilicon nitride. Other types of material capable of trapping electronsincluding, for example, tantalum oxide, strontium titanate and hafniumoxide, can also be used.

The gates 206 are fabricated using polycide material, for example. Themethod of forming the polycide layer includes forming a dopedpolysilicon layer 206 a over the substrate 200 and then forming asilicide layer 206 b over the doped polysilicon layer 206 a. Thesilicide layer 206 b is formed, for example, by performing aself-aligned silicide process or directly depositing silicide materialin a chemical vapor deposition process. The cap layer 208 is a siliconoxide layer formed, for example, by performing a chemical vapordeposition process.

Then, a plurality of insulating spacers 210 is formed on the sidewallsof the memory units 202. The insulating spacers 210 are silicon nitridelayers formed, for example, by performing an anisotropic etchingoperation so that only the insulating material layers next to thesidewalls of the memory units 202 are retained.

As shown in FIG. 2B, a plurality of memory units 216 is formed in thegaps 209 between the memory units 202. Each memory unit 216 includes acomposite layer 212 and a gate 214 sequentially formed over thesubstrate 200, for example. The composite layer 212 includes a bottomdielectric layer 212 a, a charge-trapping layer 212 b and a topdielectric layer 212 c, for example. The bottom dielectric layer 212 ais a silicon oxide layer formed, for example, by performing a thermaloxidation process. The charge-trapping layer 212 b is a silicon nitridelayer formed, for example, by performing a chemical vapor depositionprocess. The top dielectric layer 212 c is a silicon oxide layer formed,for example, by performing a chemical vapor deposition process.Obviously, the bottom dielectric layer 212 a and the top dielectriclayer 212 c can be fabricated using other material having similarproperties. Moreover, the material constituting the charge-trappinglayer 212 b is also not limited to silicon nitride. Other types ofmaterial capable of trapping electrons including, for example, tantalumoxide, strontium titanate and hafnium oxide, can also be used.

The gate 214 completely fills the gap 209 between two adjacent memoryunits 202. The gate 214 is a doped polysilicon layer formed, forexample, by depositing undoped polysilicon material over the substrateand performing an ion implant process to dope the undoped polysiliconlayer thereafter. The memory units 216 together with the memory units202 form a memory cell array 217.

After that, a source region 218 and a drain region 220 are formed in thesubstrate 200 on the respective sides of the memory cell array 217. Themethod of forming the source region 218 and the drain region 220includes removing any residual gate 214 material on the area designatedfor forming the source region and the drain region and performing an ionimplant process. In the ion implant process, either P-type ions orN-type ions are implanted depending upon the desired state of thedevice.

As shown in FIG. 2C, an inter-layer insulating layer 230 is formed overthe substrate 200. The inter-layer insulating layer 230 is patterned toform a trench 232 and a plurality of trenches 234. The trench 232exposes the source region 218 while the trenches 234 expose the gate 214of the memory units 216 in the same column. The inter-layer insulatinglayer 230 is a silicon oxide layer or other insulating material layerformed, for example, by performing a chemical vapor deposition process.The method of patterning the inter-layer insulating layer 230 includesperforming a photolithographic process and then performing ananisotropic etching operation to form the trenches 232 and 234.

As shown in FIG. 2D, a conductive layer (not shown) is formed over thesubstrate 200. The conductive layer completely fills the trenches 232and 234. Then, a portion of the conductive layer is removed until theinter-layer insulating layer 230 is exposed so that a source line 236 isformed in the trench 232 and a plurality of conductive lines 238 isformed in the respective trenches 234. The conductive layer isfabricated using tungsten and formed by performing a chemical vapordeposition process. The method of removing a portion of the conductivelayer includes performing a chemical-mechanical polishing operation, forexample. After that, another inter-layer insulating layer 240 is formedover the substrate 200.

As shown in FIG. 2E, a conductive plug 242 in contact with the drainregion 220 is formed in the inter-layer insulating layer 240 and theinter-layer insulating layer 230. The method of forming the conductiveplug 242 includes, for example, forming a contact opening (not shown) inthe inter-layer insulating layer 240 and the inter-layer insulatinglayer 230 to expose the drain region 220. Then, a conductive materialsuch as tungsten or copper is deposited into the contact opening. Anyredundant conductive material is removed until the inter-layerinsulating layer 240 is exposed to form the conductive plug 242. Themethod of removing the redundant conductive material includes, forexample, performing a back etching operation or a chemical-mechanicalpolishing operation. Thereafter, a bit line 250 in contact with theconductive plug 242 is formed over the inter-layer insulating layer 240.

In the aforementioned method of fabricating the non-volatile memory, theprocess of patterning the first inter-layer insulating layer 230 mayinclude the fabrication of the trenches 232 and 234. The source line 236and the plurality of conductive lines 238 for connecting with the gates214 can also be fabricated in the same step. Thus, without increasingthe number of processing steps, the electrical resistance of the gates214 of the memory unit 216 is reduced due to the formation of theconductive lines 238. Hence, there is an increase in the conductivity ofthe device.

In the following, the non-volatile memory structure fabricated accordingto the present invention is described in detail. FIG. 2E is a schematiccross-sectional view showing the structure of a non-volatile memoryaccording to the present invention.

As shown in FIG. 2E, the memory includes a substrate 200, a plurality ofmemory units 202, a plurality of memory units 216, a plurality ofinsulating spacers 210, a source region 218, a drain region 220, aninter-layer insulating layer 230, a source line 236, a conductive line(a metallic line) 238, an inter-layer insulating layer 240 and a bitline 250.

The memory units 202 are disposed on the substrate 200. The memory units202 are separated from one another through a gap 209. Each memory unit202 includes a composite layer 204, a gate 206 and a cap layer 208sequentially formed over the substrate 200. The composite layer 204further includes a bottom dielectric layer 204 a, a charge-trappinglayer 204 b and a top dielectric layer 204 c, for example. The bottomdielectric layer 204 a, the charge-trapping layer 204 b and the topdielectric layer 204 c are silicon oxide layer, silicon nitride layerand silicon oxide layer respectively, for example. The gate 206 isfabricated using polycide material, for example. The gate 206 includes adoped polysilicon layer 206 a and a silicide layer 206 b, for example.The cap layer 208 is fabricated using silicon oxide, for example.

The memory units 216 are disposed in the gaps 209 between the memoryunits 202. Each memory unit 216 includes a composite layer 212 and agate 214 sequentially formed over the substrate 200. The composite layer212 includes a bottom dielectric layer 212 a, a charge-trapping layer212 b and a top dielectric layer 212 c, for example. The bottomdielectric layer 212 a, the charge-trapping layer 212 b and the topdielectric layer 212 c are silicon oxide layer, silicon nitride layerand silicon oxide layer respectively, for example. The gate 214 isfabricated using doped polysilicon, for example. The insulating spacers210 are disposed between the memory units 202 and the memory units 216.The insulating spacers 210 are fabricated using silicon oxide or siliconnitride or a suitable insulating material, for example. The memory units216 together with the memory units 202 form a memory cell array 217.

The source region 218 and the drain region 220 are disposed in thesubstrate 200 on the respective sides of the memory cell array 217. Theinter-layer insulating layer 230 is disposed on the substrate 200. Thesource line 236 is disposed in the inter-layer insulating layer 230 andconnected to the source region 218. The conductive lines (metalliclines) 238 are disposed in the inter-layer insulating layer 230 andconnected with the gate 214 of the memory units 216 in the same columnso that the electrical resistance of the gates 214 is reduced. Thesource line 236 and the conductive lines (the metallic lines) 238 arefabricated using a conductive material such as tungsten or aluminum, forexample. The inter-layer insulating layer 240 is disposed over theinter-layer insulating layer 230. The bit line 250 is disposed on theinter-layer insulating layer 240 and is electrically connected to thedrain region 220 through a conductive plug 242. The inter-layerinsulating layer 230 and the inter-layer insulating layer 240 arefabricated using silicon oxide, silicon nitride or other suitableinsulating material, for example. The conductive plug 242 is fabricatedusing a conductive material such as tungsten or aluminum, for example.

In the aforementioned embodiment, the setting of the conductive lines238 over the gates 214 of the memory units 216 can reduce the electricresistance of the gates 214. This prevents the gate 214 from having ahigher electrical resistance and problems related to a low electricalconductivity when the gates 214 are fabricated from doped polysiliconmaterial alone. Hence, the difference in electrical performance betweenthe memory units 216 and the memory units 202 (whose gates arefabricated using highly conductive polycide material) is minimized. As aresult, the efficiency and stability of the device is improved.

FIGS. 3A through 3D are schematic cross-sectional views showing thesteps for fabricating a non-volatile memory according to anotherpreferred embodiment of the present invention. FIG. 3E is a top view ofa non-volatile memory according to one preferred embodiment of thepresent invention.

FIG. 3A is a continuation from FIG. 2B after the memory cell array 217has already been formed over the substrate 200 and the source region 218and the drain region 220 have already been formed in the substrate 200on the respective sides of the memory cell array 217. As shown in FIG.3A, an inter-layer insulating layer 310 is formed over the substrate200. Then, a source line 312 for connecting with the source region 218is formed in the inter-layer insulating layer 310. The inter-layerinsulating layer 310 is fabricated using an insulating material such assilicon oxide or silicon nitride, for example. The method of forming theinter-layer insulating layer 310 includes, for example, performing achemical vapor deposition process. The source line 312 is formed, forexample, by performing photolithographic and etching processes and thendepositing conductive material such as tungsten or copper to form thesource line 312 that connects with the source region 218.

As shown in FIG. 3B, another inter-layer insulating layer 320 is formedover the inter-layer insulating layer 310. Next, the inter-layerinsulating layer 320 and the inter-layer insulating layer 320 arepatterned to form a plurality of contact openings 322 and a plurality ofcontact openings 324. The method of patterning the inter-layerinsulating layer 320 and the inter-layer insulating layer 310 includesperforming a photolithographic process and then an anisotropic etchingoperation. The contact openings 322 expose the source line 312 while thecontact openings 324 expose the gate 214 of the memory units 216.

As shown in FIG. 3C, a plurality of conductive plugs 326 is formed inthe respective contact openings 322 and a plurality of conductive plugs328 is formed in the respective contact openings 324. The conductiveplugs 326 and 328 are fabricated using a conductive material such astungsten or aluminum, for example. The method of forming the conductiveplugs 326 and 328 includes performing a chemical vapor depositionprocess to deposit a layer of conductive material and then performing anetching back operation or a chemical-mechanical polishing operation toremove any redundant conductive material layer.

Then, a conductive line 330 and a plurality of conductive lines 332 areformed on the inter-layer insulating layer 320. The conductive line 330connects with the conductive plug 326 while the conductive lines 332connect with corresponding conductive plugs 328 in the same column suchthat the conductive plugs 328 in the same column are separated from oneanother by several memory units 216 (as shown in FIG. 3E). Theconductive lines 330 and 332 are fabricated using a conductive materialsuch as copper-aluminum alloy. Since the method of forming theconductive lines 330 and 332 should be familiar to those skilled in thisfield, detailed description is omitted.

As shown in FIG. 3D, another inter-layer insulating layer 340 is formedover the substrate 200. A conductive plug 342 in contact with the drainregion 220 is formed in the inter-layer insulating layer 340, theinter-layer insulating layer 320 and the inter-layer insulating layer310. After that, a bit line 350 in contact with the conductive plug 342is formed on the inter-layer insulating layer 340. FIG. 3E is a top viewof a non-volatile memory according to one preferred embodiment of thepresent invention. The device isolation structure 201 a is set up in thesubstrate for defining an active region 201 b.

In the aforementioned method of fabricating the non-volatile memory, theprocess of fabricating the conductive plug 328 and the process offabricating the conductive plug 326 that connects with the source line312 can be integrated together to simplify their productions.Furthermore, using the conductive line 332 to connect with theconductive plug 328 is capable of increasing the conductivity of thegate 214 so that the electrical performance of the memory units 216 isimproved.

In the following, the non-volatile memory structure fabricated accordingto the present invention as shown in FIG. 3D, where FIG. 3D is astructural cross-section along line E-E′ in FIG. 3E, is described.

The non-volatile memory includes a substrate 200, a plurality of memoryunits 202, a plurality of memory units 216, a plurality of insulatingspacers 210, a source region 218, a drain region 220, an inter-layerinsulating layer 310, a source line 312, an inter-layer insulating layer320, a conductive plug 328, a conductive plug 326, a conductive line(metallic line) 332, a conductive line 330, an inter-layer insulatinglayer 340, a conductive plug 342 and a bit line 350.

The memory units 202 are disposed on the substrate 200. The memory units202 are separated from one another through a gap 209. Each memory unit202 includes a composite layer 204, a gate 206 and a cap layer 208sequentially formed over the substrate 200. The composite layer 204further includes a silicon oxide layer, a silicon nitride layer andanother silicon oxide layer, for example. The gate 206 is fabricatedusing polycide material, for example. The gate 206 includes a dopedpolysilicon layer 206 a and a silicide layer 206 b, for example. The caplayer 208 is fabricated using silicon oxide, for example.

The memory units 216 are disposed in the gaps 209 between the memoryunits 202. Each memory units 216 includes a composite layer 212 and agate 214 sequentially formed over the substrate 200. The composite layer212 includes a silicon oxide layer, a silicon nitride layer and anothersilicon oxide layer, for example. The gate 214 is fabricated using dopedpolysilicon, for example. The insulating spacers 210 are disposedbetween the memory units 202 and the memory units 216. The insulatingspacers 210 are fabricated using silicon oxide, silicon nitride or asuitable insulating material, for example. The memory units 216 togetherwith the memory units 202 form a memory cell array 217.

The source region 218 and the drain region 220 are disposed in thesubstrate 200 on the respective sides of the memory cell array 217. Theinter-layer insulating layer 310 is disposed on the substrate 200. Theinter-layer insulating layer 310 is fabricated using an insulatingmaterial such as silicon oxide or silicon nitride, for example. Thesource line 312 is disposed in the inter-layer insulating layer 310 andconnected to the source region 218. The inter-layer insulating layer 320is disposed on the inter-layer insulating layer 310. The conductive plug326 is disposed in the inter-layer insulating layer 320 for connectingwith the source line 312. The conductive plugs 328 are disposed in theinter-layer insulating layer 320 and the inter-layer insulating layer310 for connecting with the gate 214 of the memory units 216. As shownin FIG. 3E, the conductive plugs 328 in the same column are separatedfrom one another by a few memory units 216 such as four memory units216. Obviously, the number of memory units 216 between two adjacentconductive plugs 328 can be eight or sixteen according to the actualdesign of the device. The conductive plugs 326 and 328 are fabricatedusing a conductive material such as tungsten or aluminum, for example.

The inter-layer insulating layer 340 is disposed on the inter-layerinsulating layer 320. The conductive lines (metallic lines) 332 and 330are disposed within the inter-layer insulating layer 340. The conductivelines (the metallic lines) 332 connect with the gate 214 of the memoryunit 216 in the same column through the conductive plugs 328; and theconductive line 330 connects with the source lines 312 through theconductive plug 326. The conductive lines (the metallic lines) 332 andthe conductive line 330 are fabricated using a conductive material suchas copper-aluminum alloy, for example.

In the aforementioned embodiment, the conductive plugs 328 are formed onthe gate 214 of the memory units 216 and the conductive plugs 328 in thesame column are connected through the conductive line 332. This preventsthe gate 214 from having a higher electrical resistance and problemsrelated to a low electrical conductivity when the gates 214 arefabricated from doped polysilicon material alone. Hence, the differencein electrical performance between the memory units 216 and the memoryunits 202 (whose gates are fabricated using highly conductive polycidematerial) is minimized. As a result, the efficiency and stability of thedevice is improved.

The non-volatile memory structure (as shown in FIG. 3D) in the presentembodiment differs from the structure in the previous embodiment (asshown in FIG. 2E). In this embodiment, a conductive plug 328 is formedbetween the conductive line 332 and the gate 214. Furthermore, theconductive line 332 connects with the gate 214 of the memory units 116in the same column. With this arrangement, the resistance at the gate214 is reduced so that the conductivity of the memory units 216 isincreased.

In summary, the process of forming conductive lines 238 on the gates 214or connecting the gates 214 of the memory units 216 in the same columnto the conductive plug 328 through a conductive line 332 can beintegrated with the processes in the source region to simplify themanufacturing steps. Furthermore, both non-volatile memory structures inthe present invention can reduce the electrical resistance of the gates214 and minimize gate conductivity problems. Hence, the difference inelectrical performance between the memory units 216 and the memory units202 (whose gates are fabricated using highly conductive polycidematerial) is minimized. As a result, the efficiency and stability of thedevice is improved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A method of fabricating a non-volatile memory, comprising the stepsof: providing a substrate; forming a plurality of first memory unitsseparated from one another by gaps on the substrate, wherein each firstmemory unit comprises a first composite layer, a first gate and a caplayer sequentially formed over the substrate; forming a plurality ofinsulating spacers on the sidewalls of the first memory units; forming aplurality of second memory units in the gaps between the first memoryunits, wherein each second memory unit comprises a second compositelayer and a second gate sequentially formed on the substrate, and thesecond memory units together with the first memory units form a memorycell array; forming a source region and a drain region in the substrateon the respective sides of the memory cell array; forming a firstinter-layer insulating layer on the substrate; patterning the firstinter-layer insulating layer to form a first trench and a plurality ofsecond trenches, wherein the first trench exposes the source region andthe second trenches expose the respective second gates of the secondmemory units in the same column; forming a conductive layer over thesubstrate, wherein the conductive layer completely fills the firsttrench and the second trenches; removing a portion of the conductivelayer until the first inter-layer insulating layer is exposed so that asource line is formed in the first trench and a plurality of conductivelines is formed in the respective second trenches; forming a secondinter-layer insulating layer over the substrate; forming a conductiveplug in contact with the drain region in the second inter-layerinsulating layer and the first inter-layer insulating layer; and forminga bit line in contact with the conductive plug over the secondinter-layer insulating layer.
 2. The method of claim 1, wherein thematerial constituting the first gate comprises polycide.
 3. The methodof claim 1, wherein the material constituting the second gate comprisesdoped polysilicon.
 4. The method of claim 1, wherein the materialconstituting the source line and the conductive line comprises tungsten.5. The method of claim 1, wherein the step of removing a portion of thefirst conductive layer until the first inter-layer insulating layer isexposed comprises performing a chemical-mechanical polishing operation.6. The method of claim 1, wherein the first composite layer comprises asilicon oxide/silicon nitride/silicon oxide composite layer.
 7. Themethod of claim 1, wherein the second composite layer comprises asilicon oxide/silicon nitride/silicon oxide composite layer.
 8. A methodof fabricating a non-volatile memory, comprising the steps of: providinga substrate; forming a plurality of first memory units separated fromone another by a gap on the substrate, wherein each first memory unitcomprises a first composite layer, a first gate and a cap layersequentially formed over the substrate; forming a plurality ofinsulating spacers on the sidewalls of the first memory units; forming aplurality of second memory units in the gaps between the first memoryunits, wherein each second memory unit comprises a second compositelayer and a second gate sequentially formed on the substrate, and thesecond memory units together with the first memory units form a memorycell array; forming a source region and a drain region in the substrateon the respective sides of the memory cell array; forming a firstinter-layer insulating layer on the substrate; forming a source linethat connects with the source region in the first inter-layer insulatinglayer; forming a second inter-layer insulating layer over the firstinter-layer insulating layer; patterning the second inter-layerinsulating layer and the first inter-layer insulating layer to form aplurality of first contact openings and a plurality of second contactopenings, wherein the first contact openings expose the source line andthe second contact openings expose the second gate of the second memoryunits; forming a plurality of first conductive plugs inside the firstcontact openings and forming a plurality of second conductive plugsinside the second contact openings; forming a first conductive line anda plurality of second conductive lines over the second inter-layerinsulating layer, wherein the first conductive line connects with thefirst conductive plug and the second conductive lines connect with thesecond conductive plugs in the same column; forming a third inter-layerinsulating layer over the substrate; forming a third conductive plug incontact with the drain region in the third inter-layer insulating layer,the second inter-layer insulating layer and the third inter-layerinsulating layer; and forming a bit line in contact with the thirdconductive plug over the third inter-layer insulating layer.
 9. Themethod of claim 8, wherein the material constituting the firstconductive plug and the second conductive plugs comprises tungsten. 10.The method of claim 8, wherein the material constituting the firstconductive line and the second conductive lines comprisescopper-aluminum alloy.
 11. The method of claim 8, wherein the firstcomposite layer comprises a silicon oxide/silicon nitride/silicon oxidecomposite layer.
 12. The method of claim 8, wherein the second compositelayer comprises a silicon oxide/silicon nitride/silicon oxide compositelayer.